1. Technical Field of the Invention
The present invention relates to a semiconductor device tester and a test method of a semiconductor device and, particularly, to an IC tester capable of obtaining a desired test signal waveform by restricting ringing thereof due to multiple reflection, which occurs between a pin electronics circuit of the tester and a semiconductor device under test (DUT), which is a semiconductor IC connected to the pin electronics circuit through a transmission line.
2. Description of the Related Art
In an IC tester, an operation test or performance test, etc., of a DUT by driving a predetermined terminal of the DUT by supplying a predetermined voltage signal thereto, determining a level of a response signal waveform output from an output terminal or an input/output terminal of the DUT, which is received by the tester after a predetermined time, by a judge circuit according to a strobe signal generated with a predetermined timing in a judge mode and comparing the level of the response signal waveform with an expected value.
An operating clock frequency of a recent DUT is in a high frequency range and an output waveform frequency thereof is also high. Therefore, an IC tester is connected through a transmission line for high frequency, such as coaxial cable, to respective terminals of the DUT. Consequently, waveform ringing occurs by multiple reflection between a feeding side and a receiving side of the transmission line, which is a problem of a high frequency circuit. This problem becomes severe in a case where an output waveform obtained at an output terminal of the DUT is judged on the IC tester side without terminating the transmission line, through which the output waveform is received, with a matching impedance, since, in such case, a waveform distortion occurs by reflection waves due to impedance mismatching between an output impedance of the DUT and an impedance of the transmission line.
In order to eliminate the effect of signal waveform ringing due to multiple reflection of a response waveform output from a DUT in a pin electronics circuit of a conventional IC tester designed on the basis of the assumption that a transmission line itself is not driven and merely connects an input/output (I/O) terminal of the DUT to a TTL or CMOS device, there is a technique proposed in the Association of Electronics, Information and Communications Engineers of Japan, Technical Report ICD92-121(1992), 45-50. According to the proposed technique, an erroneous judgement of signal level, due to ringing of a response waveform, in an analog comparator of a judge circuit of an IC tester for judging an output waveform level is prevented by removing the ringing by injecting current from a load current injection circuit (dynamic load), which is provided in the IC tester as a standard equipment, to the side of a load (DUT).
FIGS. 9(a) and 9(b) show a reflection diagram of the prior art IC tester and a response waveform from the DUT as the load, respectively, for explaining the multiple reflection and generation of ringing in such IC tester. In FIG. 9(a), abscissa indicates current I and ordinate indicates voltage V and, in FIG. 9(b), an input waveform (response waveform from the DUT) at an input terminal of the analog comparator for judging the level of the output waveform is shown.
In FIG. 9(a), since an input resistance of the analog comparator is very large as shown by a thick line 100 on the voltage axis and is usually in a range from several hundreds k.OMEGA. to several tens M.OMEGA., its current/voltage characteristics can be considered as on the ordinate. On the other hand, since the characteristic impedance Zo of a transmission line such as coaxial cable is usually 50.OMEGA., a current/voltage characteristics of the transmission line becomes as shown by a line 101. Further, since an output resistance of the DUT whose impedance is being reduced recently is in a range from several .OMEGA. to several tens .OMEGA., current/voltage characteristics of the DUT when the output of the DUT is changed from H to L becomes as shown by a thick line 102.
The change of the output voltage of the DUT from H to L is realized through a plurality of points. That is, in response to a first reflection wave, a point H on the line 100 along the voltage line at the input terminal of the comparator is shifted to a cross point 1 of the characteristic line 101, which is the characteristic impedance of the transmission line, and the output characteristic line 102 of the DUT and, then, shifted from the point 2 to a cross point 2 of the input characteristic line 100 of the analog comparator and the characteristic line 101 in response to a second reflection wave. Further, in response to a third reflection wave, it is shifted from the point 2 to a cross point 3 of a line parallel to the characteristic impedance line 101 and the output characteristic line 102 of the DUT, and so on. As a result, the H level of the input terminal of the comparator reaches a L level through a route H -1-2-3-4-5- L. Representing this on a graph having abscissa as time and ordinate as voltage, the input waveform of the comparator becomes a ringing waveform as shown in FIG. 9(b).
It is assumed in the judge circuit of the IC tester, which receives such response waveform, that the analog comparator for judging a level of the output waveform has a Low level judge voltage 103 shown by a dotted line in FIG. 9(b). The judge voltage 103 is 0.4V in a case where the DUT is a memory such as DRAM and an output of the DUT such as logic, etc., is substantially 0V. Therefore, the response waveform 104 of the DUT at the input terminal of the analog comparator exceeds the Low level judge voltage 103 in the 4 state shown in FIG. 9(b). If the analog comparator performs the low level judgement with this timing, a result thereof becomes erroneous.
In order to avoid such situation, the judgement is performed in a judge mode set by supplying a load current in a range, for example, from ten and several mA to several tens mA, which is predetermined according to the H and L output waveforms, from a constant current source to specific output terminals as injection current from the dynamic load. However, the dynamic load is originally provided in the IC tester in order to supply a load current to the output terminal of the DUT to thereby reproduce a dummy load of the DUT when the DUT is under test. The load current is different from the current for preventing the ringing. Therefore, the dynamic load is used to either provide the dummy of the DUT or prevent the ringing. The load current supply circuit (dynamic load) is usually connected to an output of the driver on the transmission line side or to the input terminal of the comparator through a diode switch.
The diode switch is usually constructed with a diode bridge and controls the supply of the load current by ON-OFF controlling the diode bridge according to the H and L outputs at the output terminal. In this respect, the diode switch is kept in OFF state in other time than the judge mode.
In the pin electronics circuit of TTL or CMOS, which is based on non-termination scheme and performs the waveform judgement by receiving the response waveform from the DUT through the transmission line, multiple reflection occurs in receiving the response waveform at the analog comparator, which is the judge circuit. Therefore, the ringing due to the multiple reflection exceeds the comparison level of the analog comparator and causes the erroneous judgement unless the current for preventing the ringing is injected from the dynamic load with a good timing.
On the other hand, the conventional dynamic load is constructed with the diode bridge and the constant current source, as mentioned previously. Therefore, electric power is always consumed in the dynamic load in the judge mode even when current is not injected to the side of the DUT (load).
When such diode bridge is utilized, diodes whose leak current is small must be used in such diode bridge. Therefore, in the conventional IC tester, the diode switch portion of the dynamic load must be provided as a discrete circuit. Further, since a number of pin electronics circuits are used, the size of the IC tester becomes large due to the provision of such discrete circuit.
Further, since, when the diode switch portion is constructed with such discrete circuit, the length of the wiring between the diode switch (diode bridge) and the buffer circuit becomes large, a high speed response becomes impossible if the output signal frequency becomes high, causing a high precision measurement to become impossible.
Incidentally, the characteristic impedance of the transmission line in the standard IC tester is 50.OMEGA., as mentioned previously. Assuming that the output amplitude of the DUT is 5V and its output impedance is 10.OMEGA., an initial under-shoot of the ringing shown at the point 2 in FIG. 9(b) becomes close to 4V. The value of the injection current from the dynamic load, which is required to cancel out such large under-shoot, becomes as large as 80 mA.
Therefore, power consumption of the whole IC tester utilizing the diode bridge and, hence, heat generation thereof becomes large. Consequently, the high precision test becomes difficult.